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document number: mc33972 rev. 9.0, 4/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. multiple switch detection interface with suppressed wake-up the 33972 multiple switch dete ction interface with suppressed wake-up is designed to detect the closing and opening of up to 22 switch contacts. the switch status, ei ther open or closed, is transferred to the microprocessor unit (mcu) through a serial peripheral interface (spi). the device also features a 22- to-1 analog multiplexer for reading inputs as analog. the analog input signal is buffered and provided on the amux output pin for the mcu to read. the 33972 device has two modes of operation, normal and sleep. normal mode allows programming of the device and supplies switch contacts with pullup or pulldown current as it monitors switch change of state. the sleep mode provides low quiescent current, which makes the 33972 ideal for automotive and industrial products requiring low sleep state currents. features ? designed to operate 5.5 v v pwr 26 v ? switch input voltage range -14 v to v pwr , 40 v max ? interfaces directly to mpu using 3.3 v / 5.0 v spi protocol ? selectable wake-up on change of state ? selectable wetting current (16 ma or 2.0 ma) ? 8 programmable inputs (switches to battery or ground) ? 14 switch-to-ground inputs ? typical standby current - v pwr = 100 a and v dd = 20 a ? active interrupt ( int ) on change-of-switch state ? pb-free packaging designated by suffix code ew figure 1. 33972 simplified application diagram multiple switch detection interface dwb suffix ew suffix (pb-free) 98arh99137a 32-pin soicw ordering information device temperature range (t a ) package mc33972dwb/r2 -40c to 125c 32 soicw mc33972ew/r2 MCZ33972Aew/r2 33972a 33972 33972 v bat v bat sp0 sp1 sp7 sg0 sg1 sg12 sg13 vpwr vdd amux wake gnd int so si sclk cs mcu an0 int miso mosi sclk cs power supply lvi watchdog reset enable v bat v dd v dd
analog integrated circuit device data 2 freescale semiconductor 33972 device variations device variations table 1. device variations device switch input voltage range reference location 33972 -14 to 38 v dc 6 33972a -14 to 40 v dc 6
analog integrated circuit device data freescale semiconductor 3 33972 internal block diagram internal block diagram figure 2. 33972 simplifi ed internal block diagram + ? 5.0 v 125 k ? v dd analog mux output v pwr , v dd , 5.0 v por oscillator clock control bandgap sleep pwr 40 a spi interface and control wake control int control temperature monitor and control mux interface sp0 sp1 sg0 sp2 sp3 sp4 sp5 sp6 sp7 sg2 sg1 sg3 sg4 sg5 sg6 sg7 sg8 sg9 sg10 sg11 sg12 sg13 wake int sclk cs so amux si vdd vpwr gnd v pwr 5.0 v v pwr 5.0 v 5.0 v v pwr v dd v dd and 5.0 v + ? 4.0 v comparator to v pwr sg0 spi ref 2.0 ma 16.0 ma v pwr 5.0 v 125 k ? v dd 2.0 + ? 4.0 v comparator to v pwr sp7 spi ref ma 2.0 ma 16.0 ma 16.0 ma v pwr 2.0 + ? 4.0 v comparator to v pwr sp0 spi ref ma 2.0 ma 16.0 ma 16.0 ma v pwr + ? 4.0 v comparator to v pwr sg13 spi ref 2.0 ma 16.0 ma v pwr
analog integrated circuit device data 4 freescale semiconductor 33972 pin connections pin connections figure 3. 33972 pin connections table 2. 33972 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name formal name definition 1 gnd ground ground for logic, analog, and switch to battery inputs. 2 si spi slave in spi control data input pin from mcu to 33972. 3 sclk serial clock spi control clock input pin. 4 cs chip select spi control chip select input pin from mcu to 33972. logic [0} allows data to be transferred in. 5 ? 8 25 ? 28 sp0 ? 3 sp4 ? 7 programmable switches 0 ? 7 programmable switch-to-battery or switch-to-ground input pins. 9 ? 15, 18 ? 24 sg0 ? 6, sg13 ? 7 switch-to-ground inputs 0 ? 13 switch-to-ground input pins. 16 vpwr battery input battery supply input pin. pin requires external reverse battery protection. 17 wake wake-up open drain wake-up output. designed to control a power supply enable pin. 29 int interrupt open-drain output to mcu. used to indicate input switch change of state. 30 amux analog multiplex output analog multiplex output. 31 vdd voltage drain supply 3.3 / 5.0 v supply. sets spi communication level for so driver. 32 so spi slave out provides digital data from 33972 to mcu. so 1 sp7 sp6 sp5 sp4 sg7 sg8 sg9 sg10 sg11 sg13 wake sg12 int vdd amux gnd sp0 sp1 sp2 sp3 sg0 sg1 sg2 sg3 sg4 sg6 vpwr sg5 cs si sclk 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31
analog integrated circuit device data freescale semiconductor 5 33972 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings vdd supply voltage cs , si, so, sclk, int , amux (1) ? -0.3 to 7.0 v dc wake (1) ? -0.3 to 40 v dc vpwr supply voltage (1) ? -0.3 to 50 v dc vpwr supply voltage at -40c (1) ? -0.3 to 45 v dc switch input voltage range ? -14 to 40 v dc frequency of spi operation (v dd = 5.0 v) ? 6.0 mhz esd voltage (3) human body model (2) applies to all non-input pins machine model charge device model corner pins interior pins v esd 2000 2000 200 750 500 v thermal ratings operating temperature ambient junction case t a t j t c - 40 to 125 - 40 to 150 - 40 to 125 c storage temperature t stg - 55 to 150 c power dissipation (t a = 25 c) (4) p d 1.7 w thermal resistance junction to ambient junction to lead r ja r jl 74 25 c/w peak package reflow temperature during reflow (5) , (6) t pprt note 6. c notes 1. exceeding these limits may cause malf unction or permanent damage to the device. 2. esd data available upon request. 3. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), and esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 4. maximum power dissipation at t j = 150 c junction temperature with no heat sink used. 5. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33972 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 3.1 v v dd 5.25 v, 8.0 v v pwr 16 v, -40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit power input supply voltage supply voltage range quasi-functional (7) fully operational supply voltage range quasi-functional (7) v pwr ( qf ) v pwr ( fo ) v pwr ( qf ) 5.5 8.0 26 ? ? ? 8.0 26 38/40 v supply current all switches open, normal mode, tri-state disabled i pwr ( on ) ? 2.0 4.0 ma sleep state supply current scan timer = 64 ms, switches open i pwr ( ss ) 40 70 100 a logic supply voltage v dd 3.1 ? 5.25 v logic supply current all switches open, normal mode i dd ? 0.25 0.5 ma sleep state logic supply current scan timer = 64 ms, switches open i dd ( ss ) ? 10 20 a switch input pulse wetting current switch-to-battery (current sink) i pulse 12 15 18 ma pulse wetting current switch-to-ground (current source) i pulse 12 16 18 ma sustain current switch-to-battery input (current sink) i sustain 1.8 2.0 2.2 ma sustain current switch-to-ground input (current source) i sustain 1.8 2.0 2.2 ma sustain current matching between channels on switch-to-ground i/os i match ? 2.0 4.0 % input offset current when selected as analog i offset -2.0 1.4 2.0 a input offset voltage when selected as analog v (sp&sginputs) to amux output v offset -10 2.5 10 mv analog operational amplifier output voltage sink 250 a v ol ? 10 30 mv analog operational amplifier output voltage source 250 a v oh v dd - 0.1 ? ? v switch detection threshold 33972 / 33972a v th 3.70 4.0 4.3 v switch input voltage range 33972 33972a v in -14 -14 ? ? 38 40 v temperature monitor (8) , (9) t lim 155 ? 185 c temperature monitor hysteresis (9) t lim(hys) 5.0 10 15 c notes 7. device operational. table paramet ers may be out of specification. 8. thermal shutdown of 16 ma pullup and pulldown current sources only. 2.0 ma current source / sink and all other functions remain active. 9. this parameter is guaranteed by design but is not production tested. i sus(max) - i sus(min) i sus(min) x 100
analog integrated circuit device data freescale semiconductor 7 33972 electrical characteristics static electrical characteristics digital interface input logic voltage thresholds (10) v inlogic 0.8 ? 2.2 v sclk, si, tri-state so input current 0 v to v dd i sclk, i si, i so (tri) -10 ? 10 a cs input current cs = v dd i cs -10 ? 10 a cs pullup current cs = 0 v i cs 30 ? 100 a so high-state output voltage i so (high ) = -200 a v so (high ) v dd - 0.8 ? v dd v so low-state output voltage i so (high ) = 1.6 ma v so (low ) ? ? 0.4 v input capacitance on sclk, si, tri-state so (11) c in ? ? 20 pf int internal pullup current ? 15 40 100 a int voltage int = open circuit v int (high) v dd - 0.5 ? v dd v int voltage i int = 1.0 ma v int (low) ? 0.2 0.4 v wake internal pullup current i wake (pu) 20 40 100 a wake voltage wake = open circuit v wake (high) 4.0 4.3 5.3 v wake voltage i wake = 1.0 ma v wake ( low ) ? 0.2 0.4 v wake voltage maximum voltage applied to wake through external pullup v wake ( max ) ? ? 40 v notes 10. upper and lower logic threshold voltage levels apply to si, cs , and sclk. 11. this parameter is guaranteed by design but is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 3.1 v v dd 5.25 v, 8.0 v v pwr 16 v, -40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33972 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 3.1 v v dd 5.25 v, 8.0 v v pwr 16 v, -40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit switch input pulse wetting current time t pulse (on) 15 16 20 ms interrupt delay time normal mode t int-dly ? 5.0 16 s sleep mode switch scan time t scan 100 200 300 s calibrated scan timer accuracy sleep mode t scan timer ? ? 10 % calibrated interrupt timer accuracy sleep mode t int timer ? ? 10 % digital interface timing (12) required low-state duration on v pwr for reset (13) v pwr 0.2 v t reset ? ? 10 s falling edge of cs to rising edge of sclk required setup time t lead 100 ? ? ns falling edge of sclk to rising edge of cs required setup time t lag 50 ? ? ns si to falling edge of sclk required setup time t si (su) 16 ? ? ns falling edge of sclk to si required hold time t si (hold) 20 ? ? ns si, cs , sclk signal rise time (14) t r (si) ? 5.0 ? ns si, cs , sclk signal fall time (14) t f (si) ? 5.0 ? ns time from falling edge of cs to so low impedance (15) t so (en) ? ? 55 ns time from rising edge of cs to so high impedance (16) t so (dis) ? ? 55 ns time from rising edge of sclk to so data valid (17) t valid ? 25 55 ns notes 12. these parameters are guaranteed by design. production test equipment uses 4.16 mhz, 5.0 v spi interface. 13. this parameter is guaranteed by design but not production tested. 14. rise and fall time of incoming si, cs , and sclk signals suggested for design consideration to prevent the occurrence of double pulsing. 15. time required for valid output status data to be available on so pin. 16. time required for output states data to be terminated at so pin. 17. time required to obtain valid data out from so following the rise of sclk with 200 pf load.
analog integrated circuit device data freescale semiconductor 9 33972 electrical characteristics timing diagrams timing diagrams figure 4. spi timing characteristics figure 5. sleep mode to normal mode operation . figure 6. normal mode interrupt operation t so(dis) 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t so(en) t si(su) t si(hold) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd vpwr vdd wake int cs sgn power-up sleep sleep mode normal mode sleep command sleep mode normal mode sleep command wake-up from interrupt timer expire wake-up from closed switch command normal mode tri-state command (disable tri-state) int cs sgn switch open ?0? 1 sgn bit in spi word switch closed ?1? 1 0 0 1 switch command 0 on falling edge of cs latch switch status switch state change with cs low generates int switch state change with cs low generates int rising edge of cs does not clear int because state change occurred while cs was low status switch command status switch command status switch command status switch command status switch command status
analog integrated circuit device data 10 freescale semiconductor 33972 functional description introduction functional description introduction the 33972 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep / wake-up modes and a robust interface between switch contacts and a microprocessor. the 33972 replaces many of the discrete components required when interfacing to microprocessor- based systems while providing switch ground offset protection, contact wetting current, and system wake-up. the 33972 features 8-program mable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. all switch inputs may be read as analog inputs through the analog multiplexer (amux). other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up /interrupt bits, and programmable wetting current settings. this device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. functional pin description chip select ( cs ) the system mcu selects the 33972 to receive communication using the chip select ( cs ) pin. with the cs in a logic low state, command words may be sent to the 33972 via the serial input (si) pin, and switch status information can be received by the mcu via the serial output (so) pin. the falling edge of cs enables the so outpu t, latches the state of the int pin, and the state of t he external switch inputs. rising edge of the cs initiates the following operation: 1. disables the so driver (high impedance) 2. int pin is reset to logic [1], except when additional switch changes occur during cs low. (see figure 6 on page 9 .) 3. activates the received command word, allowing the 33972 to act upon new data from switch inputs. to avoid any spurious data, it is essential the high-to- low and low-to-high transitions of the cs signal occur only when sclk is in a logic low state. internal to the 33972 device is an active pullup to v dd on cs . in sleep mode the negative edge of cs (v dd applied) will wake up the 33972 device. data received from the device during cs wake-up may not be accurate. system clock (sclk) the system clock (sclk) pi n clocks the internal shift register of the 33972. the si data is latched into the input shift register on the falling edge of sclk signal. the so pin shifts the switch status bits out on the rising edge of sclk. the so data is available for the mcu to read on the falling edge of sclk. false clocking of the shift register must be avoided to ensure validity of data. it is essential the sclk pin be in a logic low state whenever cs makes any transition. for this reason, it is reco mmended, though not necessary, that the sclk pin is commanded to a logic low state as long as the device is not accessed and cs is in a logic high state. when the cs is in a logic high state, any signal on the sclk and si pins will be ignored and the so pin is tri-state. spi slave in (si) the si pin is used for serial instruction data input. si information is latched into the input register on the falling edge of sclk. a logic high state present on si will program a one in the command word on the rising edge of the cs signal. to program a complete word, 24 bits of information must be entered into the device. spi slave out (so) the so pin is the output from the shift register. the so pin remains tri-stated until the cs pin transitions to a logic low state. all open switches are reported as zero , all closed switches are reported as one . the negative transition of cs enables the so driver. the first positive transition of sclk will make the status data bit 24 available on the so pin. each successive positive clock will make the next status data bit available for the mcu to read on the falling edge of sclk. the si / so shifting of the data follows a first-in, first-out protocol, with both input and output words transferring the most significant bit (msb) first. interrupt ( int ) the int pin is an interrupt output from the 33972 device. the int pin is an open-drain output with an internal pullup to v dd . in normal mode, a switch state change will trigger the int pin (when enabled). the int pin and int bit in the spi register are latched on the falling edge of cs . this permits the mcu to determine the origin of the interrupt. when two 33972 devices are used, only the device initiating the interrupt will have the int bit set. the int pin is cleared on the rising edge of cs . the int pin will not clear with rising edge of cs if a switch contact change has occurred while cs was low. in a multiple 33972 device system with wake high and v dd on (sleep mode), the falling edge of int will place all 33972s in normal mode.
analog integrated circuit device data freescale semiconductor 11 33972 functional description functional pin description wake-up ( wake ) the wake pin is an open-drain output and a wake-up input. the pin is designed to control a power supply enable pin. in the normal mode, the wake pin is low. in the sleep mode, the wake pin is high. the wake pin has a pullup to the internal + 5.0 v supply. in sleep mode with the wake pin high, falling edge of wake will place the 33972 in normal mode. in sleep mode with v dd applied, the int pin must be high for negative edge of wake to wake up the device. if v dd is not applied to the device in sleep mode, int does not affect wake operation. battery input (vpwr) the vpwr pin is battery input and power-on reset to the 33972 ic. the vpwr pin requires external reverse battery and transient protection. maxi mum input voltage on vpwr is 50 v. all wetting, sustain, and internal logic current is provided from the vpwr pin. voltage drain supply (vdd) the vdd input pin is used to determine logic levels on the microprocessor interface (spi) pins. current from vdd is used to drive so output and the pullup current for cs and int pins. vdd must be applied for wake-up from negative edge of cs or int . ground (gnd) the gnd pin provides ground for the ic as well as ground for inputs programmed as switch-to-battery inputs. programmable switches (sp0 : sp7) the 33972 device has 8 switch inputs capable of being programmed to read switch-t o-ground or switch-to-battery contacts. the input is compared with a 4.0 v reference. when programmed to be switch-t o-battery, voltages greater than 4.0 v are considered closed. voltages less than 4.0 v are considered open. the opposite holds true when inputs are programmed as switch-to-ground. programming features are defined in table 6 through table 11 in the functional device operation section of this datasheet beginning on page 12 . voltages greater than the vpwr supply voltage will source current through the sp inputs to the vpwr pin. transient battery voltages greater than 38/40 v must be clamped by an external device. switch-to-ground inputs (sg0 : sg13) the sgn pins are switch-to-ground inputs only. the input is compared with a 4.0 v reference. voltages greater than 4.0 v are considered open. voltages less than 4.0 v are considered closed. programmi ng features are defined in table 6 through table 11 in the functional device operation section of this datasheet beginning on page 12 . voltages greater than the vpwr supply voltage will source current through the sg inputs to the vpwr pin. transient battery voltages greater than 40 v must be clamped by an external device.
analog integrated circuit device data 12 freescale semiconductor 33972 functional device operation operational modes functional device operation operational modes mcu interface description the 33972 device directly interfaces to a 3.3 v or 5.0 v microcontroller unit (mcu). spi se rial clock frequencies up to 6.0 mhz may be used for programming and reading switch input status (production tested at 4.16 mhz). figure 7 illustrates the configuration between an mcu and one 33972. serial peripheral interface (spi) data is sent to the 33972 device through the si input pin. as data is being clocked into the si pin, status information is being clocked out of the device by the so output pin. the response to a spi command will always return the s witch status, interrupt flag, and thermal flag. input switch states are latched into the so register on the falling edge of the chip select ( cs ) pin. twenty-four bits are required to complete a transfer of information between the 33972 and the mcu. figure 7. spi interface with microprocessor two or more 33972 devices may be used in a module system. multiple ics may be spi-configured in parallel or serial. figures 8 and 9 show the configurations. when using the serial configur ation, 48-clock cycles are required to transfer data in / out of the ics. figure 8. spi parallel interface with microprocessor figure 9. spi serial interface with microprocessor 33972 mc68hcxx microcontroller receive buffer parallel ports to logic 24-bit shift register shift register mosi si miso so sclk cs int int parallel ports mc68hcxx microcontroller 33972 33972 si sclk cs int si so sclk cs int int sclk miso mosi shift register so parallel ports mc68hcxx microcontroller 33972 33972 si sclk cs int si so sclk cs int so int sclk miso mosi shift register
analog integrated circuit device data freescale semiconductor 13 33972 functional device operation operational modes power supply the 33972 is designed to operate from 5.5 v to 40 v on the vpwr pin. characteristics are provided from 8.0 v to 16 v for the device. switch contact currents and the internal logic supply are generated from the vpwr pin. the vdd supply pin is used to set the spi communication voltage levels, current source for the so driver, and pullup current on int and cs . vdd supply may be removed from the device to reduce quiescent current. if v dd is removed while the device is in normal mode, the device will remain in normal mode. if v dd is removed in sleep mode, the device will remain in sleep mode until wake-up input is received ( wake high to low, switch input or inte rrupt timer expires). removing v dd from the device disables spi communication and will not allow the device to wake up from int and cs pins. power-on reset (por) applying v pwr to the device will cause a power-on reset and place the device in normal mode. default settings from power-on reset via v pwr or reset command are as follows: ? programmable switch ? set to switch to battery ? all inputs set as wake-up ? wetting current on (16 ma) ? wetting current timer on (20 ms) ? all inputs tri-state ? analog select 00000 (no input channel selected) normal and sleep modes the 33972 has two operating modes, normal mode and sleep mode. a discussion on normal mode begins below. a discussion on sleep mode begins on page 18 . normal mode normal mode may be entered by the following events: ? application of v pwr to the ic ? change-of-switch state (when enabled) ? falling edge of wake ? falling edge of int (with v dd = 5.0 v and wake at logic [1]) ? falling edge of cs (with v dd = 5.0 v) ? interrupt timer expires only in normal mode with v dd applied can the registers of the 33972 be programmed through the spi. the registers that may be programmed in normal mode are listed below. further explanation of each register is provided in subsequent paragraphs. ? programmable switch register ( settings command ) ? wake-up / interrupt register ( wake-up / interrupt command ) ? wetting current register ( metallic command ) ? wetting current timer register ( wetting current timer enable command ) ? tri-state register ( tri-state command ) ? analog select register ( analog command ) ? calibration of timers ( calibration command ) ? reset ( reset command ) figure 6 , page 9 , is a graphical description of the device operation in normal mode. switch states are latched into the input register on the falling edge of cs . the int to the mcu is cleared on the rising edge of cs . however, int will not clear on rising edge of cs if a switch has closed during spi communication ( cs low). this prevents switch states from being missed by the mcu. programmable switch register inputs sp0 to sp7 may be programmable for switch-to- battery or switch-to-ground. these inputs types are defined using the settings command ( table 6 ). to set an spn input for switch-to-battery, a logic [1] for the appropriate bit must be set. to set an spn input fo r switch-to-ground, a logic [0] for the appropriate bit must be set. the mcu may change or update the programmable switch register via software at any time in normal mode. rega rdless of the setting, when the spn input switch is closed a logic [1] will be placed in the serial output response register ( table 17 , page 18 ). wake-up / interrupt register the wake-up / interrupt register defines the inputs that are allowed to wake the 33972 from sleep mode or set the int pin low in normal mode. programming the wake-up / interrupt bit to logic [0] will disable the specific input from generating an interrupt and will di sable the specif ic input from waking the ic in sleep mode ( table 7 ). programming the wake-up /interrupt bit to logic [1] will enable the specific input to generate an interrupt with s witch change of state and will enable the specific input as wake-up. the mcu may change or update the wake-up / interrupt register via software at any time in normal mode. table 6. settings command settings command not used battery/ground select 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
analog integrated circuit device data 14 freescale semiconductor 33972 functional device operation operational modes wetting current register the 33972 has two levels of switch contact current, 16 ma and 2.0 ma (see figure 10 ). the metallic command is used to set the switch contact current level ( table 8 ). programming the metallic bit to logic [0] will set the switch wetting current to 2.0 ma. programming the me tallic bit to logic [1] will set the switch contact wetting current to 16 ma. the mcu may change or update the wetting current register via software at any time in normal mode. wetting current is designed to provide higher levels of current during switch closure. the higher level of current is designed to keep switch contacts from building up oxides that form on the switch contact surface. figure 10. contact wetting and sustain current wetting current timer register each switch input has a designated 20 ms timer. the timer starts when the specific switch input crosses the comparator threshold (4.0 v). when the 20 ms timer expires, the contact current is reduced from 16 ma to 2.0 ma. the wetting current timer may be disabled for a specific input. when the timer is disabled, 16 ma of current will continue to flow through the closed switch contact. with mu ltiple wetting current timers disabled, power dissipation for the ic must be considered. the mcu may change or update the wetting current timer register via software at any time in normal mode. this allows the mcu to control the am ount of time wetting current is applied to the switch cont act. programming the wetting current timer bit to logic [0] will disable the wetting current timer. programming the wetting current timer bit to logic [1] will enable the wetting current timer ( table 9 ). tri-state register the tri-state command is use to set the spn or sgn input node as high impedance ( table 10 ). by setting the tri-state register bit to logic [1], the input will be high impedance regardless of the metallic command setting. the comparator on each input remains active. this command allows the use of each input as a comparator with a 4.0 v threshold. the mcu may change or updat e the tri-state register via software at any time in normal mode. table 7. wake-up / interrupt command wake-up /interrupt command command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 0 1 1 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 switch contact voltage 16 ma switch wetting current 2.0 ma switch sustain current 20 ms wetting current timer table 8. metallic command metallic command command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 1 0 1 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 table 9. wetting current timer enable command wetting current timer commands command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 1 0 0 0 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
analog integrated circuit device data freescale semiconductor 15 33972 functional device operation operational modes analog select register the analog voltage on switch inputs may be read by the mcu using the analog command ( table 11 ). internal to the ic is a 22-to-1 analog multiple xer. the voltage present on the selected input pin is buffer ed and made available on the amux output pin. the amux output pin is clamped to a maximum of v dd volts regardless of the higher voltages present on the input pin. after an input has been selected as the analog, the corresponding bit in the next so data stream will be logic [0]. when selecting a channel to be read as analog, the user must also set the desired current (16 ma, 2.0 ma, or high impedance). setting bit 6 and bit 5 to 0,0 selects the input as high impedance. setting bit 6 and bit 5 to 0,1 selects 2.0 ma, and 1,0 selects 16 ma. setting bit 6 and bit 5 to 1,1 in the analog select register is not allowed and will place the input as an analog input with high impedance. analog currents set by the analog command are pullup currents for all sgn and spn inputs ( table 11 ). the analog command does not allow pulldown currents on the spn inputs. setting the current to 16 ma or 2.0 ma may be useful for reading sensor inputs. further information is provided in the typical applications section of this datasheet beginning on page 20 . the mcu may change or update the analog select register via software at any time in normal mode. table 10. tri-state command tri-state commands command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 1 0 1 0 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 table 11. analog command analog command not used current select analog channel select 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 x x x x x x x x x 16 ma 2.0 ma 0 0 0 0 0
analog integrated circuit device data 16 freescale semiconductor 33972 functional device operation operational modes calibration of timers in cases where an accurate time base is required, the user may calibrate the internal timers using the calibration command ( table 13 ) . after the 33972 device receives the calibration command, the device expects 512 s logic [0] calibration pulse on the cs pin. the pulse is used to calibrate the internal clock. no other spi pins should transition during this 512 s calibration pulse. be cause the oscillator frequency changes with temperature, calibration is required for an accurate time base. calibrating the timers has no affect on the quiescent current measurement. the calibration command simply makes the time base more accurate. the calibration command may be used to update the device on a periodic basis. table 12. analog channel bits 43210 analog channel select 00000 no input selected 00001 sg0 00010 sg1 00011 sg2 00100 sg3 00101 sg4 00110 sg5 00111 sg6 01000 sg7 01001 sg8 01010 sg9 01011 sg10 01100 sg11 01101 sg12 01110 sg13 01111 sp0 10000 sp1 10001 sp2 10010 sp3 10011 sp4 10100 sp5 10101 sp6 10110 sp7 table 13. calibration command calibration command command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 x x x x x x x x x x x x x x x x
analog integrated circuit device data freescale semiconductor 17 33972 functional device operation operational modes reset the reset command resets all registers to power-on reset (por) state. refer to table 15 , page 17 , for por states or the paragraph entitled power-on reset (por) on page 13 of this datasheet. spi command summary table 15 below provides a comprehensive list of spi commands recognized by the 33972 and the reset state of each register. table 16 and table 17 contain the serial output (so) data for input voltages greater or less than the threshold level. open switches are always indicated with a logic [0], closed switches are indicated with logic [1]. table 14. reset command reset command command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x table 15. spi command summary msb command bits setting bits lsb i 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 switch status command 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x settings command bat = 1, gnd = 0 (default state = 1) 0 0 0 0 0 0 0 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 wake-up/interrupt bit wake-up = 1 non-wake-up = 0 (default state = 1) 0 0 0 0 0 0 1 0 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 0 1 1 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 metallic command metallic = 1 non-metallic = 0 (default state = 1) 0 0 0 0 0 1 0 0 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 1 0 1 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 analog command 0 0 0 0 0 1 1 0 x x x x x x x x x 16ma 0 2.0ma 0 0 0 0 0 0 wetting current timer enable command timer on = 1 timer off = 0 (default state = 1) 0 0 0 0 0 1 1 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 1 0 0 0 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 tri-state command input tri-state = 1 input active = 0 (default state = 1) 0 0 0 0 1 0 0 1 x x x x x x x x sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 1 0 1 0 x x sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 calibration command (default state ? uncalibrated) 0 0 0 0 1 0 1 1 x x x x x x x x x x x x x x x x sleep command (refer to sleep mode on page 18 .) 0 0 0 0 1 1 0 0 x x x x x x x x x x int timer int timer int timer scan timer scan timer scan timer reset command 0 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x so response will always send them flg int flg sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
analog integrated circuit device data 18 freescale semiconductor 33972 functional device operation operational modes example of normal mode operation the operation of the device in normal mode is defined by the states of the programmable internal control registers. a typical application may have the following settings: ? programmable switch ? set to switch-to-ground ? all inputs set as wake-up ? wetting current on (16 ma) ? wetting current timer on (20 ms) ? all inputs tri-state-disabl ed (comparator is active) ? analog select 00000 (no input channel selected) with the device programmed as above, an interrupt will be generated with each switch contac t change of state (open-to- close or close-to-open) and 16 ma of contact wetting current will be source for 20 ms. the int pin will remain low until switch status is acknowledged by the microprocessor. it is critical to understand int will not be cleared on the rising edge of cs if a switch closure occurs while cs is low. the maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. figure 6 , page 9 , shows the interaction between changing input states and the int and cs pins. if desired the user may disable interrupts ( wake up/ interrupt command ) from the 33972 device and read the switch states on a periodic ba sis. switch activation and deactivation faster than the mcu read rate will not be acknowledged. the 33972 device will exit the normal mode and enter the sleep mode only with a valid sleep command. sleep mode sleep mode is used to reduce system quiescent currents. sleep mode may be entered only by sending the sleep command. all register settings programmed in normal mode will be maintained in sleep mode. the 33972 will exit sleep mode and enter normal mode when any of the following events occur: ? input switch change of state (when enabled) ? interrupt timer expire ? falling edge of wake ? falling edge of int (with v dd = 5.0 v and wake at logic [1]) ? falling edge of cs (with v dd = 5.0 v) ? power-on reset (por) the v dd supply may be removed from the device during sleep mode. however removing v dd from the device in sleep mode will disable a wake-up from falling edge of int and cs . note in cases where cs is used to wake the device, the first so data message is not valid. the sleep command contains settings for two programmable timers for sleep mode, the interrupt timer and the scan timer, as shown in table 18 the interrupt timer is used as a periodic wake-up timer. when the timer expires, an interrupt is generated and the device enters normal mode. note the interrupt timer in the 33972 device may be disabled by programming the interrupt bits to logic [1 1 1]. table 19 shows the programmable settings of the interrupt timer. table 16. serial output (so) bit data type of input input programmed voltage on input pin so spi bit sp switch to ground spn < 4.0 v 1 switch to ground spn > 4.0 v 0 switch to battery spn < 4.0 v 0 switch to battery spn > 4.0 v 1 sg n/a sgn < 4.0 v 1 n/a sgn > 4.0 v 0 table 17. serial output (so) response register so response will always send them flg int flg sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 table 18. sleep command sleep command command bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 x x x x x x x x x x int timer int timer int timer scan timer scan timer scan timer
analog integrated circuit device data freescale semiconductor 19 33972 functional device operation operational modes the scan timer sets the polling period between input switch reads in sleep mode. the period is set in the sleep command and may be set to 000 (no period) to 111 (64 ms). in sleep mode when the scan timer expires, inputs will behave as programmed prior to sleep command. the 33972 will wake up for approximately 125 s and read the switch inputs. at the end of the 125 s, the input switch states are compared with the switch state prior to sleep command. when switch state changes are detected, an interrupt (when enabled; refer to wake - up / interrupt command description on page 14 ) is generated and the device enters normal mode. without switch state changes, the 33972 will reset the scan timer, inputs become tri-state, and the sleep mode continues until the scan timer expires again. table 20 shows the programmable settings of the scan timer. note the interrupt and scan timers are disabled in the normal mode. figure 5 , page 9 , is a graphical description of how the 33972 device exits sleep mode and enters normal mode. notice that the device will exit sleep mode when the interrupt timer expires or when a switch change of state occurs. the falling edge of int triggers the mcu to wake from sleep state. figure 11 illustrates the current consumed during sleep mode. during the 125 s, the device is fully active and switch states are read. the quiescent current is calculated by integrating the normal running current over scan period plus approximately 60 a. figure 11. sleep current waveform temperature monitor with multiple switch inputs closed and the device programmed with the wetting current timers disabled, considerable power will be diss ipated by the ic. for this reason temperature monitoring has been implemented. the temperature monitor is active in the normal mode only. when the ic temperature is above th e thermal limit, the temperature monitor will do all of the following: ? generate an interrupt. ? force all 16 ma pullup and pulldown current sources to revert to 2.0 ma current sources. ? maintain the 2.0 ma current source and all other functionality. ? set the thermal fl ag bit in the spi output register. the thermal flag bit in the spi word will be cleared on rising edge of cs provided the die temperature has cooled below the thermal limit. when die temperature has cooled below thermal limit, the device will resume previously programmed settings. table 19. interrupt timer bits 543 interrupt period 000 32 ms 001 64 ms 010 128 ms 011 256 ms 100 512 ms 101 1.024 s 110 2.048 s 111 no interrupt wake-up table 20. scan timer bits 210 scan period 000 no scan 001 1.0 ms 010 2.0 ms 011 4.0 ms 100 8.0 ms 101 16 ms 110 32 ms 111 64 ms inputs active for 125 us out of 32 ms i=v/r or 0.270v/100ohm = 2.7ma i=v/r or 6mv/100ohm = 60 ua inputs active for 125 us out of 32 ms i=v/r or 0.270v/100ohm = 2.7ma i=v/r or 6mv/100ohm = 60 ua inputs active for 125 us out of 32 ms i=v/r or 0.270v/100ohm = 2.7ma i=v/r or 6mv/100ohm = 60 ua i=v/r or 0.270 v/100 ? =2.7 ma inputs active for 125 s out of 32 ms i=v/r or 6.0 mv/100 ? =60 a
analog integrated circuit device data 20 freescale semiconductor 33972 typical applications introduction typical applications introduction the 33972?s primary function is the detection of open or closed switch contacts. however, there are many features that allow the device to be used in a variety of applications. the following is a list of applications to consider for the ic: sensor power supply switch monitor for metallic or elastomeric switches analog sensor inputs (ratiometric) power mosfet / led driver and monitor multiple 33972 devices in a module system the following paragraphs describe the applications in detail. sensor power supply each input may be used to supply current to sensors external to a module. many sensors such as hall effect, pressure sensors, and temper ature sensors require a supply voltage to power the sensor and provide an open collector or analog output. figure 12 shows how the 33972 may be used to supply power and interface to these types of sensors. in an application where the input ma kes continuous transitions, consider using the wake-up / interrupt command to disable the interrupt for the particular input. figure 12. sensor power supply metallic / elastomeric switch metallic switch contacts often develop higher contact resistance over time owing to contact corrosion. the corrosion is induced by humidity, salt, and other elements that exist in the environment. for this reason the 33972 provides two settings for contacts. when programmed for metallic switches, the device provides higher wetting current to keep switch contacts free of oxides. the higher current occurs for the first 20 ms of switch closure. where longer duration of wetting current is desired, the user may send the wetting current timer command and disable the timer. wetting current will be continuous to the closed switch. after the time period set by the mcu, the wetting current timer command may be sent again to enable the timer. the user must consider power dissipation on the device when disabling the timer. (refer to the paragraph entitled temperature monitor , page 19 .) to increase the amount of wetting current for a switch contact, the user has two options. higher wetting current to a switch may be achieved by paralleling sgn or spn inputs. this will increase wetting current by 16 ma for each input added to the switch contact. the second option is to simply add an external resistor pullup to the v pwr supply for switch- to-ground inputs or a resistor to ground for a switch-to-battery input. adding an external resi stor has no effect on the operation of the device. elastomeric switch contacts are made of carbon and have a high contact resistance. resistance of 1.0 k ? is common. in applications with elastomeric switches, the pullup and pulldown currents must be reduced to prevent excessive power dissipation at the contact. programming for a lower current settings is provided in the functional device operation section beginning on page 12 under table 8 , metallic command. analog sensor inputs (ratiometric) the 33972 features a 22-to-1 analog multiplexer. setting the binary code for a specific input in the analog command allows the microcontroller to perform analog to digital conversion on any of the 22 inputs. on rising edge of cs the multiplexer connects a requested input to the amux pin. the amux pin is clamped to max of v dd volts regardless of the higher voltages present on the in put pin. after an input has been selected as the analog, the corresponding bit in the next so data stream will be logic [0]. the input pin, when selected as analog, may be configured as analog with high impedance, analog with 2.0 ma pullup, or analog with 16 ma pullup. figure 13 , page 21 , shows how the 33972 may be used to provide a ratiometric reading of variable resistive input. v dd v pwr v dd si so sclk int cs mosi miso vbat sp0 sp1 sp7 sg1 sg0 sg12 sg13 wake 33972 sclk cs int mcu 16 2.0 v pwr v pwr 16 ma ioc[7:0] x reg input capture timer port hall-effect sensor 2.5 k ? ma 16 2.0 v pwr v pwr ma 2.5 k ? vbat ma ma
analog integrated circuit device data freescale semiconductor 21 33972 typical applications introduction figure 13. analog ratiometric conversion to read a potentiometer sensor, the wiper should be grounded and brought back to the module ground, as illustrated in figure 13 . with the wiper changing the impedance of the sensor, the ana log voltage on the input will represent the position of the sensor. using the analog feature to provide 2.0 ma of pullup current to an analog sensor may induce error due to the accuracy of the current source. for this reason, a ratiometric conversion must be consider ed. using two current sources (one for the sensor and one to set the reference voltage to the a / d converter) will yield a maximum error (owing to the 33972) of 4%. higher accuracy may be achieved through module level calibration. in this example, we use the resistor values from figure 13 and assume the current sources are 4% from each other. the user may use the module end-of-line tester to calculate the error in the a / d conversion. by placing a 2.0 k ? , 0.1% resistor in the end-of-line test equipment and assuming a perfect 2.0 ma current source from the 33972, a calculated a / d conversion may be obtained. us ing the equation yields the following: the adc value of 213 counts is the value with 0% error (neglecting the resistor tole rance and amux input offset voltage). now we can calculate the count value induced by the mismatch in current sources. from a sample device the maximum current source was measured at 2.05 ma and minimum current source was measured at 1.99 ma. this yields 3% error in a / d conversion. the a / d measurement will be as follows: this a / d conversion is 3% low in value. the error correction factor of 1.03 may be used to correct the value: an error correction factor may then be stored in e 2 memory and used in the a / d calculation for the specific input. each input used as analog measurement will have a dedicated calibrated error correction factor. power mosfet / led driver and monitor because of the flexible programming of the 33972 device, it may be used to drive small loads like leds or mosfet gates. it was specifically designed to power up in the normal mode with the inputs tri-state. this was done to ensure the leds or mosfets connected to the 33972 power up in the off-state. the swit ch programmable (sp0 ? sp7) inputs have a source-and-sink capability, providing effective mosfet gate control. to complete the circuit, a pulldown resistor should be used to keep the gate from floating during the sleep modes. figure 14 , page 22 , shows an application where the sg0 input is used to monitor the drain-to-source voltage of the external mosfet. the 1.5 k ? resistor is used to set the drain-to-source trip voltage. with the 2.0 ma current source enabled, an interrupt will be generated when the drain-to-source voltage is approximately 1.0 v. v dd v pwr v dd si so sclk int cs amux mosi miso an0 vbat sp0 sp1 sp7 sg1 sg0 sg12 sg13 wake vbat sclk cs int 16 2.0 v pwr 2.0 ma 2.0 ma 2.39 k ? 0.1% 4.54 v to 5.02 v analog ports v ref(h) v ref(l) analog sensor or analog switch r 2 i 2 i 1 r 1 v pwr ma 2.0 v pwr v pwr ma 16 ma ma 33972 mcu adc = i1 x r1 i2 x r2 x225 adc = 2.0 ma x 2.0 k ? x 225 2.0 ma x 2.39 k ? adc = 213 counts adc = 1.99 ma x 2.0 k ? x225 2.05 ma x 2.39 k ? adc = 207 counts adc = 207 counts x 1.03 adc = 213 counts
analog integrated circuit device data 22 freescale semiconductor 33972 typical applications introduction figure 14. mosfet or led driver output the sequence of commands (from normal mode with inputs tri-state) required to set up the device to drive a mosfet are as follows: ? wetting current timer enable command ? disable spn wetting current timer (refer to table 9 , page 14 ). ? metallic command ? set spn to 16 ma or 2.0 ma gate drive current (refer to table 8 , page 14 ). ? settings command ? set spn as switch -to-battery (refer to table 6 , page 13 ). ? tri-state command ? disable tri-state for spn (refer to table 10 , page 15 ). after the tri-state command has been sent (tri-state disable), the mosfet gate will be pulled to ground. from this point forward the mosfet may be turned on and off by sending the settings command : ? settings command ? spn as switch-to-ground (mosfet on). ? settings command ? spn as switch-to-battery (mosfet off). monitoring of the mosfet drai n in the off state provides open load detection. this is done by using an sgn input comparator. with the sgn input in tri-state, the load will pull up the sgn input to battery. wi th open load the sgn pin is pulled down to ground through an external resistor. the open load is indicated by a logic [1] in the so data bit. the analog command may be used to monitor the drain voltage in the mosfet on state. by sourcing 2.0 ma of current to the 1.5 k ? resistor, the analog voltage on the sgn pin will be approximately: as the voltage on the drain of the mosfet increases, so does the voltage on the sgn pin. with the sgn pin selected as analog, the mcu may perform the a / d conversion. using this method for controlling unclamped inductive loads is not recommended. induc tive flyback voltages greater than v pwr may damage the ic. the sp0 : sp7 pins of this device may also be used to send signals from one module to another. operation is similar to the gate control of a mosfet. ? for led applications a resistor in series with the led is recommended but not requir ed. the switch-to-ground inputs are recommended for led application. to drive the led use the following commands: ? wetting current timer enable command ? disable sgn wetting current timer. ? metallic command ? set sgn to 16 ma. from this point forward the led may be turned on and off using the tri-state command : ? tri-state command ? disable tri-state for sgn (led on). ? tri-state command ? enable tri-state for sgn (led off). these parameters are easily programmed via spi commands in normal mode. multiple 33972 devices in a module system connecting power to the 33972 and the mcu for sleep mode operation may be done in several ways. table 21 shows several system configurat ions for power between the mcu and the 33972 and their specific requirements for functionality. multiple 33972 devices may be used in a module system. spi control may be done in parallel or serial. however when parallel mode is used, each device is addressed independently (refer to mcu interface description , page 12 ). sp0 sg0 sg13 16 2.0 4.0 v ref + - comparator to spi v pwr sg0 1.5 k ? load vbat amux 100 k ? ma v pwr + - comparator to spi 4.0 v ref 2.0 2.0 ma 16 ma 16 ma v pwr v pwr sg0 16 2.0 v pwr ma v pwr + comparator to spi 4.0 v ref sg13 - ma ma ma table 21. sleep mode power supply mcu v dd 33972 v dd comments 5.0 v 5.0 v all wake-up conditions apply. (refer to sleep mode , page 18 .) 5.0 v 0 v spi wake-up is not possible. 0 v 5.0 v sleep mode not possible. current from cs pullup will flow through mcu to v dd that has been switched off. negative edge of cs will put 33972 in normal mode. 0 v 0 v spi wake-up is not possible. v sgn = i sgn x 1.5 k ? + v ds
analog integrated circuit device data freescale semiconductor 23 33972 typical applications introduction therefore when sending the sleep command , one device will enter sleep before the other. for multiple devices in a system, it is recommended that the devices are controlled in serial (s0 from first device is connected to si of second device). with two devices, 48 clock pulses are require d to shift data in. when the wake feature is used to enable the power supply, both wake pins should be connected to the enable pin on the power supply. the int pins may be connected to one interrupt pin on the mcu or may have their own dedicated interrupt to the mcu. the transition from normal to sleep mode is done by sending the sleep command . with the devices connected in serial and the sleep command sent, both will enter sleep mode on the rising edge of cs . when sleep mode is entered, the wake pin will be logic [1]. if either device wakes up, the wake pin will transition low, waking the other device. a condition exists where the mcu is sending the sleep command ( cs logic [0]) and a switch input changes state. with this event the device that detects this input will not transition to sleep mode, while the second device will enter sleep mode. in this case two switch status commands must be sent to receive accurate switch status data. the first switch status command will wake the device in sleep mode. switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 v input comparator threshold. this time is dependant on th e impedance of sgn or spn node. the second switch status command will provide accurate switch stat us information. it is recommended that software wait 10 ms to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. with all switch stat es acknowledged by the mcu, the sleep sequence may be initiated. all parameters for sleep mode should be updated prior to sending the sleep command . the 33972 ic has an internal 5.0 v supply from v pwr pin. a por circuit monitors the internal 5.0 v supply. in the event of transients on the v pwr pin, an internal reset may occur. upon reset the 33972 will enter normal mode with the internal registers as defined in table 15 , page 17 . therefore it is recommended that the mcu periodically update all registers internal to the ic. using the wake feature the 33972 provides a wake output and wake-up input designed to control an enable pin on system power supply. while in the normal mode, the wake output is low, enabling the power supply. in the sleep mode, the wake pin is high, disabling the power supply. the wake pin has a passive pullup to the internal 5.0 v supply but may be pulled up through a resistor to v pwr supply (see figure 16 , page 24 ) when the wake output is not used the pin should be pulled up to the v dd supply through a resistor as shown in figure 15 , page 24 . during the sleep mode, a switch closure will set the wake pin low, causing the 33972 to enter the normal mode. the power supply will then be activat ed, supplying power to the v dd pin and the microprocessor and the 33972. the microprocessor can determine th e source of the wake-up by reading the interrupt flag. cost and flexibility systems requiring a significant number of switch interfaces have many discrete components. discrete components on standard pwb consume board space and must be checked for solder jo int integrity. an integrated approach reduces solder joints , consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility.
analog integrated circuit device data 24 freescale semiconductor 33972 typical applications introduction figure 15. power supply active in sleep mode figure 16. power supply shutdown in sleep mode v dd mc68hcxx microprocessor 33972 vbat power mosi miso an0 wake si so sclk int cs amux vbat vbat sp0 sp1 sp7 sg1 sg0 sg12 sg13 supply vdd sclk int cs v pwr v pwr v dd v dd mc68hcxx microprocessor 33972 vbat power mosi miso an0 wake si so sclk int cs amux vbat vbat sp0 sp1 sp7 sg1 sg0 sg12 sg13 supply vdd sclk int cs enable v pwr v dd v dd v dd v pwr
analog integrated circuit device data freescale semiconductor 25 33972 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98a listed below. dwb suffix ew suffix (pb-free) 32-lead soic wide body plastic package 98arh99137a
analog integrated circuit device data 26 freescale semiconductor 33972 packaging package dimensions (continued) package dimensions (continued)
analog integrated circuit device data freescale semiconductor 27 33972 revision history revision history revision date description of changes 4.0 2/2006 ? converted to freescale format ? added pc33972a version ? changed figure 15, power supply active in sleep mode ? changed figure 16, power supply shutdown in sleep mode ? updated outline drawing for package 5.0 6/2006 ? update to the prevailing freescale form and style. 6.0 7/2006 ? added mc33972t devices. ? updated static electrical characteristics on page 6 with 33972t parameters. 7.0 11/2006 ? changed human body model parameters in maximum ratings table. ? replaced part number mc33972tew/r2 with mcz33972tew/r2 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 5 . added note with instructions to obtain this information from www.freescale.com . 8.0 12/2006 ? restated note (6) ? changed part number mcz33972tew/r2 with mc33972tew/r2 9.0 4/2007 ? removed all references to the 33972t device. ? removed the mc33972tdwb/r2, mc33972tew/r2, and pc33972aew/r2 from the ordering information. ? added MCZ33972Aew/r2 to the ordering information.
mc33972 rev. 9.0 4/2007 rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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